1. Field
This disclosure relates to error detection in electronic circuits, and, more particularly, to error detection in integrated microelectronic circuits.
2. Background Information
As is well-known, digital electronic circuitry may experience certain types of data errors. Among these types of errors, one particular type is soft-errors. Soft-errors are typically the results of external random events, such as radiation due to alpha particles or cosmic neutrons, for example, though other sources may exist. Such soft-error sources are well-known to those of skill in the art. In this regard, these external random events may cause a digital logic value to switch from its intended value, e.g. from logic xe2x80x981xe2x80x99 to logic xe2x80x980xe2x80x99. As is also well-known, soft-errors are typically transient in nature. More particularly, after the effects of a soft-error are corrected, digital electronic components will typically function as expected.
Typical approaches that are employed to detect/correct such errors include parity and error checking and correction (ECC), both of which are well-known to those of skill in the art. Such approaches are, for example, commonly employed in memory array circuits, such as static random access memory (SRAM). Such memory arrays may be included, for example, in cache memory components, which may, in turn, be employed in a variety of computing platforms. Because such memory arrays, when embodied on, for example, an integrated circuit, have repeating physical patterns or layout, such techniques typically have little area impact on such circuits because parity or ECC circuitry may be efficiently incorporated as part of such repeating patterns. Likewise, such techniques typically have little adverse performance impact on such memory components, as the time to access digital electronic signals stored in such memory arrays is typically not significantly affected by such circuitry.
In contrast, because, at a minimum, datapath circuitry typically comprises layouts that are less compact, or dense, than, for example, memory arrays, current approaches to employing such parity or ECC techniques may be difficult to implement in datapath circuitry and may, for example, result in undesirable area impacts to such circuits. These area impacts may be due, at least in part, to the fact that parity or ECC circuitry may not be efficiently incorporated, as in memory arrays, for example. Likewise, because datapath circuitry is typically performance limiting to many circuits, current approaches employing parity and ECC in datapaths typically result in undesirable adverse effects on the performance of such circuits. Therefore, based on the foregoing, alternative error detection/correction schemes for datapath circuitry may be desirable.